1. Field of the Invention
The present invention relates to analog to digital converters (ADC's), and more particularly, to reducing nonlinearities and inter-symbol interference in high-speed analog to digital converters.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution). FIG. 1 shows a generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators 107, fine comparators 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.
Modern flash, folding and subranging analog to digital converters (ADC's) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.
In general, flash, folding and subranging ADC's use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators. These residue signals are obtained by subtracting different DC reference voltages from an input signal Vin. The DC reference voltages are generated by the resistive ladder (reference ladder) 104 biased at a certain DC current.
High-resolution ADC's often use auto-zero techniques, also called offset compensation techniques, to suppress amplifier offset voltages. In general, autozeroing requires two clock phases (φ1 and φ2). During the auto-zero phase, the amplifier offset is stored on one or more capacitors, and during the amplify phase, the amplifier is used for the actual signal amplification.
Two different auto-zero techniques can be distinguished, which are illustrated in FIGS. 2 and 3. The technique shown in FIG. 2 connects an amplifier 201 in a unity feedback mode during the auto-zero clock phase φ1. As a result, a large part of the amplifier 201 input offset voltage is stored on input capacitors C1a, C1b. The remaining offset is stored on output capacitors C2a, C2b if available.
The second technique, shown in FIG. 3, shorts the amplifier 201 inputs during the auto-zero phase φ1 and connects them to a DC bias voltage Vres. Here, the amplifier 201 output offset voltage is stored on the output capacitors C2a, C2b. Many ADC architectures use a cascade of several (auto-zero) amplifiers to amplify the input signal prior to applying to the comparators 107, 108. In general, flash, folding and subranging ADC's use arrays of cascaded amplifiers, and averaging and interpolation techniques are used to improve performance.
Unfortunately, the performance of cascaded arrays of amplifiers degrades significantly at high clock and input signal frequencies. The cause of this degradation is illustrated in FIG. 4 when the reset technique shown in FIG. 3 is used, and where RSW is shown as a circuit element, and the current flow IC is explicitly shown.
When the amplifier 201 is in the auto-zero phase φ1, the input capacitors C1a, C1b are charged to the voltage Vsample that is provided by the track-and-hold amplifier 101. As a result, a current IC will flow through the input capacitors C1a, C1b and an input switch (not shown). Due to the finite on-resistance RSW of the input switch (see FIG. 4), an input voltage is generated, which will settle exponentially towards zero. This input voltage is amplified by the amplifier 201 and results in an output voltage that also slowly settles towards zero (assuming the amplifier 201 has zero offset).
Essentially, the auto-zero amplifier 201 is in a “reset” mode one-half the time, and in an “amplify” mode the other one-half the time. When in reset mode, the capacitors C1a, C1b are charged to the track-and-hold 101 voltage, and the current IC flows through the capacitors C1a, C1b and the reset switches, so as to charge the capacitors C1a, C1b. 
When the ADC has to run at high sampling rates, there is not enough time for the amplifier 201 output voltage to settle completely to zero during the reset phase. As a result, an error voltage is sampled at the output capacitors C2a, C2b that is dependent on the voltage Vsample. This translates into non-linearity of the ADC, and often causes inter-symbol interference (ISI).
The problem of ISI occurs in most, if not all, ADC architectures and various approaches exist for attacking the problem. The most straightforward approach is to decrease the settling time constants. However, the resulting increase in power consumption is a major disadvantage.
Another approach is to increase the time allowed for settling, by using interleaved ADC architectures. However, this increases required layout area. Furthermore, mismatches between the interleaved channels cause spurious tones. The ISI errors can also be decreased by resetting all cascaded amplifiers during the same clock phase. Unfortunately, this is not optimal for high speed operation either.